1. Field of the Invention
The present invention relates to a semiconductor storage device comprising a memory cell, a bit line connected to the memory cell, a precharge circuit which steps up a voltage of the bit line to a power supply voltage, and a step-down circuit which steps down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell.
2. Description of the Related Art
In the field of a semiconductor storage device, there is technology, which is conventionally available, for improving a data reading speed by stepping down a bit line precharged with a power supply voltage to a voltage level lower than the power supply voltage before data is read and thereby shortening a time required for a change in the voltage of the bit line from the power supply voltage level to a ground level. The change in the voltage of the bit line from the power supply voltage level to the ground level is detected by a PMO transistor at a subsequent gate. However, when a step-down level in the bit line is below an operation region of a transistor for detection, through current and a data-read error are thereby caused. Data-read errors also occur in the case where a sense amplifier or a PMOS cross driver is connected to the bit line. Therefore, it is necessary to set a step-down level of the bit line at around a threshold voltage of the PMOS transistor.
In a SRAM circuit where the bit line is precharged with the power supply voltage, charges of the power supply voltage level of the bit line flow into a node at which “L” data of SRAM is retained upon the activation of a word line in a non-selected column used for the data reading or writing operations. The inflow of too many charges results in the generation of a data-write error. An indicator called the static noise margin is used to show a level of resistance against data-write errors. The static noise margin has been reduced in recent years as the semiconductor is increasingly miniaturized, and consequently data-write errors are more likely to occur. In order to respond to the recent trend, there is a conventional technology wherein a potential of the power supply voltage level of the bit line is stepped down so as to reduce the current flow into the node of the memory cell at which “L” data is stored, such flow taking place when the word line is activated. When the voltage step-down level in the bit line is not enough, a data-write error occurs due to the reason described above. When the voltage step-down level in the bit line is too high, a data-write error is caused by charges of “L” level of the bit line which flow into the node of the SRAM at which “H” data of the SRAM is retained. Therefore, it is necessary to step down the voltage of the bit line to such a voltage level that can assure the static noise margin.
Below is described a technology for stepping down the voltage of the bit line in a conventional semiconductor storage device referring to FIGS. 15A and 15B. FIG. 15A is a circuit diagram illustrating a constitution of a conventional semiconductor storage device, and FIG. 15B is a timing chart illustrating an operation of the semiconductor storage device. In FIG. 15A, 11 denotes a SRAM memory cell, 12 denotes a precharge circuit, 13 denotes a reading circuit, 14 denotes a step-down circuit, BL and /BL are complementary bit lines, WL denotes a word line, PC denotes a precharge control signal, DC denotes a step-down control signal, QP51, QP52 and QP53 denote PMOS transistors constituting the precharge circuit 12, QN51 and QN52 denote NMOS transistors constituting the step-down circuit 14, QP54 denotes a PMOS transistor, and Inv denotes an inverter.
The step-down circuit 14 is additionally provided in order to step-down voltages of the bit lines BL and /BL prior to the activation of the word line WL. Sources of the step-down transistors QN51 and QN52 are connected to the ground, drains thereof are directly connected to the bit lines BL and /BL, and gates thereof are connected to a gate of the equalizing transistor QP54 via the inverter Inv. The gates of the step-down transistors QN51 and QN52 are driven by the step-down control signal DC.
As shown in FIG. 15B, prior to the activation of the word line WL, the precharge control signal PC is negated and thereby turns to “H” level at a timing t51, the precharge transistors QP51 and QP52 and the equalizing transistor QP53 are turned off, which leaves the bit lines BL and /BL in a floating state.
At a timing t52, the step-down control signal DC is asserted and thereby turns to “H” level, and the step-down transistors QN51 and QN52 in the step-down circuit 14 are turned on. Further, the equalizing transistor QP54 is turned on, charges of the bit line BL and /BL are then discharged, and potentials of the bit lines BL and /BL are stepped down to a predetermined voltage level. A possible example of the predetermined voltage level is VDD-Vth. VDD is a power supply voltage used for the precharge, and Vth is a threshold voltage of the MOS transistors.
When the step-down control signal DC is negated and thereby turns to “IL” level at a timing t53, the step-down transistors QN51 and QN52 are turned off, and the equalizing transistor QP54 is turned off. As a result, the step-down and equalizing operations for the bit lines BL and /BL are halted.
At a timing t54, the word line WL is asserted, and data is read from the memory cell 11. In the case where “0” is stored in the memory cell 11, current flows from the bit line BL into the memory cell 11, and the potential of the bit line BL is lowered; however, the potential of the complementary bit line /BL is not stepped down. The bit line BL=“L” level and the complementary bit line /BL=“H” level are judged by the reading circuit 14 as “0” data. In the case where “1” is stored in the memory cell 11, current flows from the complementary bit line /BL into the memory cell 11, and the potential of the complementary bit line /BL is lowered; however, the potential of the bit line BL is not stepped down. The bit line BL=“H” level and the complementary bit line /BL=“L” level are judged by the reading circuit 14 as “1” data. Broken lines denoting the potentials of the bit lines BL and /BL shown in FIG. 15B illustrate potential reduction irrespective of whether the potential reduction occurs at the bit line BL or the complementary bit line /BL.
At a timing t55, the word line WL is at “L” level, and the data reading operation is terminated. At a timing t56, the precharge control signal PC is asserted and thereby turns to “L” level, and the precharge transistors QP51 and QP52 and the equalizing transistor QP53 are turned on. Then, the bit lines BL and /BL are precharged with the power supply voltage.
In the foregoing description, the step-down levels of the bit lines BL and /BL are adjusted in accordance with a pulse width of the step-down control signal DC. Provided that the step-down level is ΔV, and the pulse width of the step-down control signal DC is Tw, ΔV ∝ Tw, which means that the step-down level ΔV is substantially in proportion with the pulse width Tw of the step-down control signal DC.
In general, the voltages of the bit lines BL and /BL are stepped down prior to the activation of the word line WL in an initial stage of an operation cycle. The word line WL is activated shortly after the operation cycle starts. Therefore, the step-down transistors QN51 and QN52 are controlled by the step-down control signal DC having a fine pulse width. In the foregoing conventional technology, the step-down level ΔV in the bit lines BL and /BL are decided in a sensitive manner by the pulse width Tw of the step-down control signal DC inputted to the step-down transistors QN51 and QN52. Therefore, when the pulse width Tw of the step-down control signal DC changes depending on operation conditions and device variability, the step-down level ΔV varries significantly, which results in a malfunction.